Free PDF Logic Circuit Design: Selected Methods By Shimon P. Vingron
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Logic Circuit Design: Selected Methods By Shimon P. Vingron
Free PDF Logic Circuit Design: Selected Methods By Shimon P. Vingron
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- Amazon Sales Rank: #3673477 in eBooks
- Published on: 2012-03-28
- Released on: 2012-03-28
- Format: Kindle eBook
Review
From the reviews:
“In this book on logic circuit design (emphasis on ‘circuit’), the author reworks and expands the treatment provided in his earlier text, Switching theory: insight through predicate logic … . it will no doubt prove to be useful to engineers, circuit designers, etc., for its well-chosen examples and its ‘non-traditional’ emphasis on the underlying hardware realization problems of logic circuit design.” (Ronald E. Prather, Mathematical Reviews, January, 2013)
From the Back Cover
In three main divisions the book covers combinational circuits, latches, and asynchronous sequential circuits. Combinational circuits have no memorising ability, while sequential circuits have such an ability to various degrees. Latches are the simplest sequential circuits, ones with the shortest memory. The presentation is decidedly non-standard. The design of combinational circuits is discussed in an orthodox manner using normal forms and in an unorthodox manner using set-theoretical evaluation formulas relying heavily on Karnaugh maps. The latter approach allows for a new design technique called composition. Latches are covered very extensively. Their memory functions are expressed mathematically in a time-independent manner allowing the use of (normal, non-temporal) Boolean logic in their calculation. The theory of latches is then used as the basis for calculating asynchronous circuits. Asynchronous circuits are specified in a tree-representation, each internal node of the tree representing an internal latch of the circuit, the latches specified by the tree itself. The tree specification allows solutions of formidable problems such as algorithmic state assignment, finding equivalent states non-recursively, and verifying asynchronous circuits.
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